In wireless communication systems 100 such as exemplary illustrated in FIG. 1 data typically needs to be exchanged between the communication processor 101 also referred to as modem and the application processor 103 at high data rates. To allow such high data rates, a layer 2 (L2) buffer on the CP memory 105 is used for buffering data packets. However, CP memory 105 space is limited and used for storing data and code. It is thus desirable to provide a concept for reducing the L2 buffer space on the CP memory 105 without impacting the data rates between CP 101 and AP 103.